In a multi-processor system, or multi-core processor system, some variables are shared by all cores of the processor or by all processors within the system. Conventionally, updates to shared variables go through a globally unique serialization point. For example, hardware cache coherency and a semaphore system are often needed to maintain consistency of a shared variable during a read-modify-write operation. For certain types of variables, such as those that are updated often but read infrequently, multiple processors contend with one another to update the variable in the shared memory. And memory contentions result in reduced performance either because of retries or blocking conditions. For example, where a shared counter is read by a first processor, access to the shared counter by a second processor is blocked. The second processor waits for the shared memory to become available before completing its update operation. In another example, such as may occur in a reduced instruction set computing (RISC) architecture, software reads a variable and then attempts to write to the same variable. But if another access to the variable occurs after the first read, the hardware will not perform the subsequent write.